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| 19-4558; Rev 0; 4/09 3.3V Dual-Output LVPECL Clock Oscillator General Description The DS4625 is a dual-output, low-jitter clock oscillator capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5.0mm x 3.2mm surface-mount LCCC package. Standard frequency options are listed in the Ordering Information/Selector Guide table. For custom frequency options, contact the factory at: Custom.Oscillators@maxim-ic.com. The DS4625 provides dual, low-voltage, positive emitter-coupled logic (LVPECL) clock output drivers. The output drivers can be enabled and disabled through the OE pin, which is an active-high CMOS input that has an internal pullup resistor. When high, both output pairs are enabled. The device operates from a single +3.3V 10% supply. The operating temperature range is -40C to +70C. Features Standard Clock Output Frequencies: 100MHz, 125MHz, 150MHz, 156.25MHz, and 200MHz Phase Jitter < 0.7ps RMS (typical) from 12kHz to 20MHz LVPECL Output +3.3V 10% Operating Voltage -40C to +70C Temperature Range Excellent Power-Supply Noise Rejection 5.0mm x 3.2mm Ceramic LCCC Package Output Enable/Disable DS4625 Applications XGMII Clock Oscillator InfiniBandTM SAS/SATA PCIe(R) 1GbE/10GbE Ordering Information/Selector Guide PART DS4625P+100/150 DS4625P+125/125 DS4625P+125/156 DS4625P+150/150 DS4625P+150/200 TEMP RANGE -40C to +70C -40C to +70C -40C to +70C -40C to +70C -40C to +70C FREQUENCY (OP1:ON1) (MHz) (fC)* 100.000 125.000 125.000 150.000 150.000 FREQUENCY (OP2:ON2) (MHz) (fC)* 150.000 125.000 156.250 150.000 200.000 PIN-PACKAGE 10 LCCC 10 LCCC 10 LCCC 10 LCCC 10 LCCC TOP MARK 6AC 6BB 6BD 6CC 6CE +Denotes a lead(Pb)-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. *Standard frequency options. Contact the factory at Custom.Oscillators@maxim-ic.com for custom frequencies. Pin Configuration and Typical Application Circuit appear at end of data sheet. InfiniBand is a trademark and service mark of the InfiniBand Trade Association. PCIe is a registered trademark of PCI-SIG Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 3.3V Dual-Output LVPECL Clock Oscillator DS4625 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to ground unless otherwise noted.) Voltage Range on Any Pin Relative to Ground......-0.3V to +4.0V Operating Temperature Range ...........................-40C to +70C Junction Temperature ......................................................+150C JA ...................................................................+90C/W (Note 1) Storage Temperature Range ...............................-55C to +85C Soldering Temperature (3 passes max of reflow)......Refer to the IPC/JEDEC J-STD-020 Specification. Note 1: Package thermal resistances were obtained using a two-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER Operating Voltage Range Input-Voltage High (OE) Input-Voltage Low (OE) SYMBOL VCC VIH VIL CONDITIONS MIN 2.97 0.7 x VCC 0 TYP 3.3 MAX 3.63 VCC 0.3 x VCC UNITS V V V ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +3.63V, TA = -40C to +70C, typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 2, 3) PARAMETER Operating Current SYMBOL ICC_PU ICC_PL ICC_OEZ Output Frequency Startup Time Frequency Stability Frequency Stability Over Temperature with Initial Tolerance Initial Tolerance Frequency Change Due to VCC Frequency Change Due to Load Variation Aging (15 Years) OE Pullup Resistance f OUT1 f OUT2 t START fTOTAL/fC CONDITIONS LVPECL, output unloaded LVPECL, output loaded VOE = V IL VOE = V IH (Note 4) Temperature, aging, load, supply, and initial tolerance (Note 5) VCC = +3.3V -50 MIN TYP 65 120 80 fC 1.0 +50 MAX 90 140 115 UNITS mA mA mA MHz ms ppm fTEMP/fC -35 20 -3 1 -7 +35 ppm ppm f INITIAL/fC VCC = +3.3V, TA = +25C f VCC fLOAD/fC fAGING/fC RPU TA = +25C VCC = +3.3V 10%, TA = +25C 10% variation in termination resistance +3 ppm/V ppm +7 100 130 ppm k 70 2 _______________________________________________________________________________________ 3.3V Dual-Output LVPECL Clock Oscillator ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.97V to +3.63V, TA = -40C to +70C, typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 2, 3) PARAMETER Output High Voltage Output Low Voltage Differential Output Voltage Output Rise Time Output Fall Time Duty Cycle Propagation Delay from OE Going Low to Output High Impedance Propagation Delay from OE Going High to Output Active Jitter Accumulated Deterministic Jitter Due to Reference Spurs Accumulated Deterministic Jitter Due to Power-Supply Noise (P-P) (Note 6) SYMBOL VOH VOL |V OD | tR tF DCYCLE t PAZ (See Figure 2) CONDITIONS Output connected to 50 VCC - 2.0V Output connected to 50 VCC - 2.0V Output connected to 50 VCC - 2.0V 20% to 80% 80% to 20% 45 at PECL_BIAS at at PECL_BIAS at at PECL_BIAS at MIN VCC 1.085 VCC 1.825 0.595 0.710 200 200 55 100 TYP MAX VCC 0.88 VCC 1.62 UNITS V V V ps ps % ns DS4625 t PZA JRMS (See Figure 2) Integrated phase RMS, 12kHz to 20MHz, VCC = +3.3V, TA = +25C 125.00MHz output, VCC = +3.3V, TA = +25C 10kHz 100kHz 200kHz 1MHz 0.7 0.1 12.9 26.3 20.1 6.4 100 ns ps ps ps ps ps ps Note 2: Note 3: Note 4: Note 5: Note 6: Limits at -40C are guaranteed by design and are not production tested. AC parameters are guaranteed by design and not production tested. Startup time is from VCC = VCCMIN until PLL locks to the crystal oscillator output. Frequency stability is calculated as: fTOTAL = fTEMP + fVCC x (3.3 x 10%) + fLOAD + fAGING. Supply-induced jitter is the deterministic jitter as measured on a LeCroy SDA11000 measured with a 50mVP-P sine wave forced on VCC. SINGLE-SIDEBAND PHASE NOISE SSB PHASE NOISE (dBc/Hz) (TYPICAL, +25C, +3.3V) OFFSET 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 20MHz fC = 100MHz -71 -116 -119 -126 -143 -151 -151 fC = 125MHz -85 -117 -118 -125 -142 -149 -150 fC = 150MHz -84 -116 -116 -122 -141 -149 -149 fC = 156.25MHz -79 -115 -117 -123 -140 -148 -149 fC = 200MHz -85 -113 -113 -120 -139 -149 -150 dBc/Hz UNITS _______________________________________________________________________________________ 3 3.3V Dual-Output LVPECL Clock Oscillator DS4625 Typical Operating Characteristics (TA = +25C, unless otherwise noted.) fC DEVIATION vs. TEMPERATURE 40 30 DEVIATION (ppm) 20 10 0 -10 -20 -30 -40 -50 -40 -20 0 20 40 60 TEMPERATURE (C) 0 3.0 3.1 DS4625 toc01 fC DEVIATION vs. VCC DS4625 toc02 ICC vs. VCC 130 120 ICC_PU DS4625 toc03 50 3.0 2.5 DEVIATION (ppm) 2.0 1.5 1.0 0.5 140 CURRENT (mA) 110 100 90 80 70 60 50 ICC_PL ONE OUTPUT LOADED 3.2 3.3 VCC (V) 3.4 3.5 3.6 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5 3.6 Pin Description PIN 1 2, 3 4 5 6 A1, A2 A3 A4 -- NAME OE GND OP1 ON1 VCC N.C. OP2 ON2 EP Ground Positive Output 1 for LVPECL Negative Output 1 for LVPECL Supply Voltage Input No Internal Connection. Must be connected to ground. Positive Output 2 for LVPECL Negative Output 2 for LVPECL Exposed Pad. The exposed pad must be used for thermal relief. This pad must be connected to ground. FUNCTION Active-High Output Enable. Has an internal pullup resistor (RPU). 4 _______________________________________________________________________________________ 3.3V Dual-Output LVPECL Clock Oscillator DS4625 VCC VCC RPU X1 OE X0 PLL LC-VCO X2 PFD LPF DIV M LVPECL ON1 DIV N OP2 OP1 DS4625 DIV P LVPECL ON2 GND Figure 1. Block Diagram 0.7 x VCC OE 0.3 x VCC tPZA tPAZ OP_ PECL_BIAS PECL_BIAS ON_ PECL_BIAS PECL_BIAS Figure 2. LVPECL Output Timing Diagram When OE is Enabled and Disabled _______________________________________________________________________________________ 5 3.3V Dual-Output LVPECL Clock Oscillator DS4625 Pin Configuration TOP VIEW N.C. N.C. A2 6 VCC Detailed Description The DS4625 is a dual-output, low-jitter clock oscillator that produces frequency output pair combinations as shown in the Ordering Information/Selector Guide table. The phase relationship between the outputs is not guaranteed. The device combines an AT-cut, fundamentalmode crystal, an oscillator, and a low-noise PLL in a 5.0mm x 3.2mm surface-mount LCCC package. The DS4625 provides dual LVPECL clock output drivers. The output drivers can be enabled and disabled through the OE pin. The OE pin is an active-high CMOS input that has an internal pullup resistor. When OE is high, both output pairs are enabled. + OE 1 A1 GND 2 DS4625 5 ON1 GND 3 *EP A3 A4 4 OP1 Chip Information PROCESS: Bipolar SiGe OP2 ON2 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 10 LCCC PACKAGE CODE L1053+H2 DOCUMENT NO. 21-0389 (5.00mm x 3.20mm x 1.49mm) *EXPOSED PAD Typical Application Circuit VCC 0.1F 0.01F OP1 50 PECL_BIAS AT VCC - 2.0V DS4625 50 ON1 OE OP2 50 GND 50 ON2 PECL_BIAS AT VCC - 2.0V Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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